2017-10-26 19:35 厂商:nuvoton 申请截止日期: 2018-10-26 23:59
 NUC970 Series Features
ARM® ARM926EJ-S™ processor core runs up to 300 MHz
Support 16 KB instruction cache and 16 KB data cache
Support MMU
Support JTAG Debug interface
External Bus Interface (EBI)
Support SRAM and external I/O devices
Support 8/16-bit data bus width
Support up to five chip selects for SRAM and external I/O devices
Support programmable access cycle
Support four 32-bit write buffers
DDR SDRAM Controller
Clock speed up to 150 MHz
Support 16-bit data bus width
Support two chip selects
Support total memory size up to 256M bytes (each chip select for 128M bytes)
Embedded SRAM and ROM
Support 56K bytes embedded SRAM
Support 16K bytes Internal Boot ROM (IBR)
Support up to four booting modes
Boot from USB
Boot from eMMC
Boot from NAND Flash
Boot from SPI Flash
Clock Control
Support two PLLs, up to 500 MHz, for high performance system operation
External 12 MHz high speed crystal input for precise timing operation
External 32.768 kHz low speed crystal input for RTC function and low speed clock
Ethernet MAC Controller
Support up to 2 Ethernet MAC controllers
Support IEEE Std. 802.3 CSMA/CD protocol
Support packet time stamping for IEEE Std. 1588 protocol
Support 10 and 100 Mbps operations
Support Half- and Full-duplex operations
Support RMII interface to Ethernet physical layer PHY
Support Ethernet physical layer PHY management through MDC and MDIO interface
Support flow control in Full-duplex mode to receive, recognize and transmit PAUSE
Support CAM-like function to recognize 48-bit Ethernet MAC address
Support Wake-On-LAN by detecting Magic Packet
Support 256 bytes transmit FIFO and 256 bytes receive FIFO
Support DMA function
Support internal loop back mode for diagnostic
USB 2.0 Controller  
Support USB Revision 2.0 specification
Support one set of USB 2.0 High-Speed (HS) Device/Host with embedded transceiver
Support one set of USB 2.0 High-Speed (HS) Host with embedded transceiver
Support Control, Bulk, Interrupt, Isochronous and Split transfers
Support USB host function compliant to Enhanced Host Controller Interface (EHCI) 1.0
specification to connect with USB 2.0 High-Speed (HS) device.
Support USB host function compliant to Open Host Controller Interface (OHCI) 1.0
specification to connect with USB 1.1 Full-Speed (FS) and Low-Speed (LS) devices
Support USB High-Speed (HS) and Full-Speed (FS) device function
Support USB device function with 1 endpoint for Control IN/OUT transfers and 12
programmable endpoints for Bulk, Interrupt and Isochronous IN/OUT transfers
Support suspend, resume and remote wake-up capability
Support DMA function
Support 2048 Bytes internal SRAM for USB host function and 4096 Bytes internal
SRAM for USB device function
Flash Memory Interface
Support NAND flash interface
Support 8-bit data bus width
Support SLC and MLC type NAND flash device
Support 512 B, 2 KB, 4 KB and 8 KB page size NAND flash device
Support ECC4, ECC8, ECC12, ECC15 and ECC24 BCH algorithm for ECC code
generation, error detection and error correction.
Support eMMC flash interface
Support DMA function to accelerate the data transfer between system memory and
NAND and eMMC flash.
I2S Controller
Support I2S interface
Support both mono and stereo
Support both record and playback
Support 8-bit, 16-bit 20-bit and 24-bit data precision
Support master and slave mode
Support PCM interface
Support 2 slots mode to connect 2 device
Support 8-bit, 16-bit 20-bit and 24-bit data precision
Support master mode
Support four 8x24 (8 24-bit) buffer for left/right channel record and left/right playback
Support DMA function to accelerate the data transfer between system memory and
internal buffer
Support 2 buffer address for left/right channel and 2 slots data transfer
LCD Display Controller
Support 8/9/16/18/24-bit data with to connect with 80/68 series MPU type LCD module
Support resolution up to 1024x768
Support data format conversion from RGB444, RGB565, RGB666, RGB888, YUV422
and YUV444 to RGB444, RGB565, RGB666, RGB888, YUV422 and YUV444 for
display output
Support CCIR-656 (with VSYNC, HSYNC and data enable sync signal) 8/16-bit YUV
data output to connect with external TV encoder
Support 8/16 bpp OSD data with video overlay function to facilitate the diverse graphic
Support linear 1X to 8X image scaling up function
Support Picture-In-Picture display function
Support hardware cursor  
Capture (CMOS Sensor Interface)
Support CCIR601 & CCIR656 interfaces to connect with CMOS image sensor
Support resolution up to 3M pixels
Support YUV422 and RGB565 color format for data output by CMOS image sensor
Support YUV422, RGB565, RGB555 and Y-only color format for data storing to system
Support planar and packet data format for data storing to system memory
Support image cropping and the cropping window is up to 4096x2048
Support image scaling-down:
Support vertical and horizontal scaling-down for preview mode
Support N/M scaling factor where N is equal to or less than M
Support 2 pairs of configurable 16-bit N and 16-bit M
Support to combine two interlace-fields to a single frame for data output by TVdecoder.
Support 3 color processing effects
Negative picture
Sepia picture
2D Graphic Engine
Support 2D Bit Block Transfer (BitBLT) functions defined in Microsoft GDI
Support Host BLT
Support Pattern BLT
Support Color/Font Expanding BLT
Support Transparent BLT
Support Tile BLT
Support Block Move BLT
Support Copy File BLT
Support Color/Font Expansion
Support Rectangle Fill
Support RGB332/RGB565/RGB888 data format.
Support fore/background colors and all Microsoft 256 ternary raster-operation codes
Support both inside and outside clipping function
Support alpha-blending for source/destination picture overlaying
Support fast Bresenham line drawing algorithm to draw solid/textured line
Support rectangular border and frame drawing
Support picture re-sizing
Support down-scaling from 1/255 to 254/255
Support up-scaling from 1 to 1.996 (1+254/255)
Support object rotation with different degree
Support L45 (45 degree left rotation) and L90 (90 degree left rotation)
Support R45 (45 degree right rotation) and R90 (90 degree right rotation)
Support M180 (mirror/flop)
Support F180 (up-side-down (flip) and X180 (180 degree rotation)
JPEG Codec
Support baseline Sequential mode JPEG codec function compliant with ISO/IEC
10918-1 international JPEG standard
Planar Format
Support to encode interleaved YCbCr 4:2:2/4:2:0 and gray-level (Y only) format image
Support to decode interleaved YCbCr 4:4:4/4:2:2/4:2:0/4:1:1 and gray-level (Y only)
format image
Support to decode YCbCr 4:2:2 transpose format
Support arbitrary width and height image encode and decode 

Operating Voltage
1.2V for core logic operating
1.8V for DDR2 SDRAM I/O operating
3.3V for normal I/O operating
Operating Temperature: -40~85
All Green package (RoHS)
LQFP 216-pin
LQFP 128-pin