RK3568 HDMI_RX + LT6911UXC 音频采集

我们使用了HDMI_RX芯片，LT6911UXC现在已经调通视频采集，音频数据走的是lt6911UXC->I2S3M1->rk3568x.
我们实际的设备树配置如下：

hdmirx_sound: hdmirx-sound {
        status = "okay";
        compatible = "simple-audio-card";
        simple-audio-card,name = "rockchip,dummy-sound";
        simple-audio-card,format = "i2s";
        simple-audio-card,mclk-fs = <256>;
        simple-audio-card,cpu {
            sound-dai = <&i2s3_2ch>;
        };
        simple-audio-card,codec {
            sound-dai = <&dummy_codec>;
        };
    };
    dummy_codec: dummy-codec {
        status = "okay";
        compatible = "rockchip,dummy-codec";
        #sound-dai-cells = <0>;
    };
&i2s3_2ch {
    status = "okay";
    #sound-dai-cells = <0>;
    pinctrl-0 = <&i2s3m1_mclk
             &i2s3m1_sclk    //硬件上使用了I2S3的I2S3m1
             &i2s3m1_lrck
             &i2s3m1_sdi
             /*&i2s3m0_sdo*/>;
};

按照参考配置今后，没有发现I2S3的声卡，
[ 3.218878] ALSA device list:
[ 3.218885] #0: hdmi-sound
[ 3.218900] #1: ROCKCHIP,SPDIF
[ 3.218911] #2: rockchip,i2s1-sound
[ 3.224396] EXT4-fs (mmcblk0p6): mounted filesystem with ordered data mode. Opts: (null)
[ 3.224457] VFS: Mounted root (ext4 filesystem) on device 179:6.

另外我们也用到了RK616芯片，但是只用了LCD转HDMI视频输出，硬件上音频没有使用电阻断开了，但内核设备树上有使用 I2S3M1_CLK 这个就和LT6911UXC那边的采集冲突了，改如何去掉呢？
尝试过，将i2s3m1_mclk及clock的相关的全部注释掉，系统就起不来了。

 rk618@50 {
        compatible = "rockchip,rk618";
        reg = <0x50>;
        pinctrl-names = "default";
        pinctrl-0 = <&i2s3m1_mclk &rk618_int>;
        clocks = <&cru I2S3_MCLKOUT>;
        clock-names = "clkin";
        assigned-clocks =<&cru I2S3_MCLKOUT>, <&cru I2S3_MCLK_IOE>;
        assigned-clock-parents = <&cru I2S3_MCLKOUT_TX>, <&cru I2S3_MCLKOUT>;
        assigned-clock-rates = <11289600>;
        reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>;
        status = "okay";
        clock: cru {
            compatible = "rockchip,rk618-cru";
            clocks = <&cru I2S3_MCLKOUT>, <&cru DCLK_VOP2>;
            clock-names = "clkin", "lcdc0_dclkp";
            assigned-clocks = <&clock SCALER_PLLIN_CLK>,
            <&clock VIF_PLLIN_CLK>,
            <&clock SCALER_CLK>,
            <&clock VIF0_PRE_CLK>,
            <&clock CODEC_CLK>,
            <&clock DITHER_CLK>;
            assigned-clock-parents = <&cru I2S3_MCLKOUT_TX>,
            <&clock LCDC0_CLK>,
            <&clock SCALER_PLL_CLK>,
            <&clock VIF_PLL_CLK>,
            <&cru I2S3_MCLKOUT>,
            <&clock VIF0_CLK>;
            #clock-cells = <1>;
            status = "okay";
        };