Rockchip px30调试口uart2更改为uart3问题

请教下，PX30的默认调试口为串口2，现在想更改为串口3。请问下怎么更改，以下我更改的地方，但是仍然不行,。大神们帮忙看看问题在哪
1.ddrbin_param.txt修改点

uart id=3
uart iomux=1
uart baUDRate=115200

2.Uboot_defconfig文件修改点

CONFIG_BAUDRATE=115200
CONFIG_DEBUG_UART_BASE=0xFF168000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=3
CONFIG_ROCKCHIP_PRELOADER_SERIAL=y

px30-u-boot.dtsi修改点
chosen {
stdout-path = &uart3;
};
&uart3 {
        clock-frequency = <24000000>;
        u-boot,dm-pre-reloc;
        status = "okay";
};

px30.dtsi修改

aliases {
                serial0 = &uart0;
                serial1 = &uart1;
                serial2 = &uart2;
                serial3 = &uart3;
                i2c0 = &i2c0;
                i2c1 = &i2c1;
                i2c2 = &i2c2;
                i2c3 = &i2c3;
};

3.px30.c修改

void board_debug_uart_init(void)
{
        static struct px30_grf * const grf = (void *)GRF_BASE;

        /* GRF_IOFUNC_CON0 */
        enum {
                CON_IOMUX_UART2SEL_SHIFT        = 10,
                CON_IOMUX_UART2SEL_MASK = 3 << CON_IOMUX_UART2SEL_SHIFT,
                CON_IOMUX_UART2SEL_M0        = 0,
                CON_IOMUX_UART2SEL_M1,
                CON_IOMUX_UART2SEL_USBPHY,

                CON_IOMUX_UART3SEL_SHIFT = 9,
                CON_IOMUX_UART3SEL_MASK = 1 << CON_IOMUX_UART3SEL_SHIFT,
                CON_IOMUX_UART3SEL_M0 = 0,
                CON_IOMUX_UART3SEL_M1,
        };

    enum {
        GPIO1B7_SHIFT                = 12,
        GPIO1B7_MASK                = 0xf << GPIO1B7_SHIFT,
        GPIO1B7_GPIO                = 0,
        GPIO1B7_FLASH_RDN,
        GPIO1B7_UART3_RXM1,
        GPIO1B7_SPI0_CLK,


        GPIO1B6_SHIFT                = 8,
        GPIO1B6_MASK                = 0xf << GPIO1B6_SHIFT,
        GPIO1B6_GPIO                = 0,
        GPIO1B6_FLASH_CS1,
        GPIO1B6_UART3_TXM1,
        GPIO1B6_SPI0_CSN,
    };
    rk_clrsetreg(&grf->gpio1bh_iomux,
            GPIO1B7_MASK,
            GPIO1B7_UART3_RXM1 << GPIO1B7_SHIFT);
    rk_clrsetreg(&grf->gpio1bh_iomux,
            GPIO1B6_MASK,
            GPIO1B6_UART3_TXM1 << GPIO1B6_SHIFT);
    rk_clrsetreg(&grf->iofunc_con0,
            CON_IOMUX_UART3SEL_MASK,
            CON_IOMUX_UART3SEL_M1 << CON_IOMUX_UART3SEL_SHIFT);
#ifdef CONFIG_TPL_BUILD
        static struct px30_cru * const cru = (void *)CRU_BASE;
        static struct rk_uart * const uart = (void *)UART2_BASE;

    rk_clrsetreg(&cru->clksel_con[40],
            UART2_PLL_SEL_MASK | UART2_DIV_CON_MASK,
            UART2_PLL_SEL_24M << UART2_PLL_SEL_SHIFT | 0);
    rk_clrsetreg(&cru->clksel_con[41],
            UART2_CLK_SEL_MASK,
            UART2_CLK_SEL_UART2 << UART2_CLK_SEL_SHIFT);
        /* GRF_GPIO2BH_IOMUX */
        enum {
                GPIO2B7_SHIFT                = 12,
                GPIO2B7_MASK                = 0xf << GPIO2B7_SHIFT,
                GPIO2B7_GPIO                = 0,
                GPIO2B7_CIF_D10M0,
                GPIO2B7_I2C2_SCL,

                GPIO2B6_SHIFT                = 8,
                GPIO2B6_MASK                = 0xf << GPIO2B6_SHIFT,
                GPIO2B6_GPIO                = 0,
                GPIO2B6_CIF_D1M0,
                GPIO2B6_UART2_RXM1,

                GPIO2B5_SHIFT                = 4,
                GPIO2B5_MASK                = 0xf << GPIO2B5_SHIFT,
                GPIO2B5_GPIO                = 0,
                GPIO2B5_PWM2,

                GPIO2B4_SHIFT                = 0,
                GPIO2B4_MASK                = 0xf << GPIO2B4_SHIFT,
                GPIO2B4_GPIO                = 0,
                GPIO2B4_CIF_D0M0,
                GPIO2B4_UART2_TXM1,
        };

        /* uart_sel_clk default select 24MHz */
        rk_clrsetreg(&cru->clksel_con[37],
                     UART2_PLL_SEL_MASK | UART2_DIV_CON_MASK,
                     UART2_PLL_SEL_24M << UART2_PLL_SEL_SHIFT | 0);
        rk_clrsetreg(&cru->clksel_con[38],
                     UART2_CLK_SEL_MASK,
                     UART2_CLK_SEL_UART2 << UART2_CLK_SEL_SHIFT);

        /* Enable early UART2 */
        rk_clrsetreg(&grf->iofunc_con0,
                     CON_IOMUX_UART2SEL_MASK,
                     CON_IOMUX_UART2SEL_M1 << CON_IOMUX_UART2SEL_SHIFT);

        /*
         * Set iomux to UART2_M0 and UART2_M1.
         * Because uart2_rxm0 and uart2_txm0 are default reset value,
         * so only need set uart2_rxm1 and uart2_txm1 here.
         */
        rk_clrsetreg(&grf->gpio2bh_iomux,
                     GPIO2B6_MASK,
                     GPIO2B6_UART2_RXM1 << GPIO2B6_SHIFT);
        rk_clrsetreg(&grf->gpio2bh_iomux,
                     GPIO2B4_MASK,
                     GPIO2B4_UART2_TXM1 << GPIO2B4_SHIFT);

        /* enable FIFO */
        writel(0x1, &uart->sfe);
#else
#ifdef CONFIG_SPL_BUILD
        /* GRF_GPIO1DL_IOMUX */
        enum {
                GPIO1D3_SHIFT                = 12,
                GPIO1D3_MASK                = 0xf << GPIO1D3_SHIFT,
                GPIO1D3_GPIO                = 0,
                GPIO1D3_SDMMC_D1,
                GPIO1D3_UART2_RXM0,

                GPIO1D2_SHIFT                = 8,
                GPIO1D2_MASK                = 0xf << GPIO1D2_SHIFT,
                GPIO1D2_GPIO                = 0,
                GPIO1D2_SDMMC_D0,
                GPIO1D2_UART2_TXM0,

                GPIO1D1_SHIFT                = 4,
                GPIO1D1_MASK                = 0xf << GPIO1D1_SHIFT,
                GPIO1D1_GPIO                = 0,
                GPIO1D1_SDIO_D3,

                GPIO1D0_SHIFT                = 0,
                GPIO1D0_MASK                = 0xf << GPIO1D0_SHIFT,
                GPIO1D0_GPIO                = 0,
                GPIO1D0_SDIO_D2,
        };

        /* Do not set the iomux in U-Boot proper because SD card may using it */
        /* Enable early UART2 channel m0 on the px30 */
        rk_clrsetreg(&grf->gpio1dl_iomux,
                     GPIO1D3_MASK | GPIO1D2_MASK,
                     GPIO1D3_UART2_RXM0 << GPIO1D3_SHIFT |
                     GPIO1D2_UART2_TXM0 << GPIO1D2_SHIFT);
#endif
        /* Set channel C as UART2 input */
        rk_clrsetreg(&grf->iofunc_con0,
                     CON_IOMUX_UART2SEL_MASK,
                     CON_IOMUX_UART2SEL_M0 << CON_IOMUX_UART2SEL_SHIFT);
#endif
}

4.内核修改

chosen {
                bootargs = "earlycon=uart8250,mmio32,0xff168000 swiotlb=1 console=ttyFIQ0 rootwait";
};

&uart3 {
        status = "disabled";
        pinctrl-names = "default";
        pinctrl-0 = <&uart3m1_xfer>;
};

fiq_debugger: fiq-debugger {
                compatible = "rockchip,fiq-debugger";
                rockchip,serial-id = <3>;
                rockchip,wake-irq = <0>;
                /* If enable uart uses irq instead of fiq */
                rockchip,irq-mode-enable = <0>;
                rockchip,baudrate = <115200>;  /* Only 115200 and 1500000 */
                interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
                pinctrl-names = "default";
                pinctrl-0 = <&uart3m1_xfer>;
                status = "okay";
};