Hi3519V101 项目讨论组进度

目前项目进展正常：
Core Board在做最后审查，因为工艺是八层二阶板子，打板价格昂贵，所以比较谨慎，下面上图,预计节后发板



hi3519V101的性能
Processor Core
800 MHz A7 core, supporting 32 KB I-cache, 32 KB Dcache,
and 128 KB L2 cache
1.25G GHz A17 core, supporting 32 KB I-cache, 32 KB
D-cache, and 256 KB L2 cache
Neon acceleration, integrated FPU

Video Encoding
H.264 BP/MP/HP
H.265 Main Profile

I/P/B frame, dual-P-frame reference
MJPEG/JPEG baseline encoding
性能：

Video Encoding Performance
Maximum 16-megapixel (4608 x 3456) resolution for
H.264/H.265 encoding

Real-time multi-stream H.264/H.265 encoding capability:
3840 x 2160@30 fps+1080p@30 fps + 3840 x 2160@2fps

snapshot
Maximum JPEG snapshot performance of 3840 x
2160@30 fps
CBR, VBR, FIXQP, AVBR, and QPMAP modes
Maximum100 Mbit/s output bit rate
Encoding of eight ROIs

智能分析：
Integrated IVE, supporting various intelligent analysis
applications such as motion detection, perimeter defense,
and video diagnosis
Video and Graphics Processing
3D denoising, image enhancement, and dynamic contrast
improvement
Anti-flicker for output videos and graphics
1/30x to 16x video scaling
Seamless splicing of 2-channel videos
1/2x to 2x graphics scaling
OSD overlaying of eight regions before encoding
Video graphics overlaying of two layers (video layer and
graphics layer)
ISP
2-channel independent ISP processing
Adjustable 3A functions (AE, AWB, and AF)
FPN removal
Highlight compensation, backlight compensation, gamma
correction, and color enhancement
Defect pixel correction, denoising, and digital image
stabilization
Anti-fog
Lens distortion correction and fisheye correction
Picture rotation by 90° or 270°
Picture mirroring and flipping
Sensor built-in WDR, 4F/3F/2F frame-based/line-based
WDR, and local tone mapping. The second channel of ISP

其它参照官方SDK