海思tw2968音频输出问题

大家好，调试tw2968的驱动时，视频与音频输入都已调试通过，现在音频输出（playback）一直没有输出，从cpu的输出量取数据线的波形都正常，只是到2968后，2968的AOUT没有输出。
现在可以确定CPU输出的信号是正常的，以下是音频的相关计算器配置，请大家帮看看：
static void tw2968_audio_init(unsigned char chip_addr)
{
    /* Analog Power Down Control */
    //tw2968_byte_write(chip_addr, 0xCE, 0x40 );

    /* 0xD0, 0xD1, 0x7F - Analog Audio Input Gain */
    tw2968_byte_write(chip_addr, 0x7f, 0x88);/* [7:4] AIGAIN5 [3:0] MIXRATIO5 */
    tw2968_byte_write(chip_addr, 0xD0, 0x88);/* [7:4] AIGAIN2 [3:0] AIGAIN1 */
    tw2968_byte_write(chip_addr, 0xD1, 0x88);/* [7:4] AIGAIN4 [3:0] AIGAIN3 */

    /* Number of Audio to be Recorded */
    tw2968_byte_write(chip_addr, 0xD2, 0x03);/* recode: I2S format, 16 audios */

    /* 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA – Sequence of Audio to be Recorded*/
    tw2968_byte_write(chip_addr, 0xD3, 0x10);/* default value: 1 0 */
    tw2968_byte_write(chip_addr, 0xD7, 0x32);/* default value: 9 8 */

    /* playback: I2S, master, 16bit, ACLKR pin is output */
    tw2968_byte_write(chip_addr, 0xDB, 0xE1);

    /* u-Law/A-Law Output and Mix Mute Control */
    tw2968_byte_write(chip_addr, 0xDC, 0x00);/* PCM output */

    /* Mix Output Selection */
    tw2968_byte_write(chip_addr, 0xE0, 0x10);/* Select playback audio of the first stage chips*/

    /* Audio Detection Threshold, 8K typical setting value */
    tw2968_byte_write(chip_addr, 0xE1, 0xf0);
    tw2968_byte_write(chip_addr, 0xE2, 0x33);
    tw2968_byte_write(chip_addr, 0xE3, 0x33);
    tw2968_set_audio_samplerate(TW2968_SAMPLE_RATE_16000);
#if 1
    /* Audio Clock Increment, ACKI[21:0]: 09B583h for fs = 8kHz is default. */
    tw2968_byte_write(chip_addr, 0xF0, 0x23);//0x23 0x91);/* ACKI[7:0] */
    tw2968_byte_write(chip_addr, 0xF1, 0x48);///* 0x48 0x8B ACKI[15:8] */
    tw2968_byte_write(chip_addr, 0xF2, 0x07);//0x07 0x30);/* ACKI[21:16] */
#endif
    /* [3] ACKI control is automatically set up by AFMD register values */
    /* [2:0] AFAUTO control mode. 0: 8kHz setting(default). */
        tw2968_byte_write(chip_addr, 0x70, 0x09);/* [2:0] 0:8k, 1:16k, 2:32k, 3:44.1k 4:48k */
        //tw2968_byte_write(chip_addr, 0x71, 0x60);

    /* Audio Clock Control */
    tw2968_byte_write(chip_addr, 0xF8, 0xc4);/* bit2: Loop open in ACKG block */

    /* Enable state register updating and interrupt request of audio AIN5 detection for each input*/
        tw2968_byte_write(chip_addr, 0x73, 0x00);

    /* ADATM I2S Output Select (default value)*/ /* Mix Digital and Analog out set to  */
    tw2968_byte_write(chip_addr, 0x7B, 0x00);/* Select record audio of channel 51(AIN51)*/
    tw2968_byte_write(chip_addr, 0x7C, 0x00);/* Select record audio of channel 51(AIN51)*/
    /* MIX_MUTE_A5 ?????? */
    tw2968_byte_write(chip_addr, 0x7E, 0xa0);
    /* Audio Fs Mode Control */
    tw2968_byte_write(chip_addr, 0x89, 0x04);/* AIN5MD=1, AFS384=0 */
}