rk628-for-all v27版本 在rk3568移植技术指导

没用过rk628，比起龙讯的怎么样？ 怎么个编译失败贴一下图片

1. 什么系统？
2. 编译驱动报错吗？

如果内核编译通过，可以参考一下这个dts配置，还有hal也要参考628的补丁包增加

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
 *
 */

/ { 
    dummy_codec: dummy-codec {
        compatible = "rockchip,dummy-codec";
        #sound-dai-cells = <0>;
        status = "okay";
    };

    hdmiin_sound: hdmiin-sound {
        compatible = "simple-audio-card";
        simple-audio-card,format = "i2s";
        simple-audio-card,name = "rockchip,hdmiin";
        simple-audio-card,bitclock-master = <&dailink0_master>;
        simple-audio-card,frame-master = <&dailink0_master>;
        status = "okay";
        simple-audio-card,cpu {
          sound-dai = <&i2s3_2ch>;
        };
        dailink0_master: simple-audio-card,codec {
          sound-dai = <&dummy_codec>;
        };
    };
};

&i2s3_2ch {
    status = "okay";
    pinctrl-0 = <&i2s3m0_sclk
                 &i2s3m0_lrck
                 &i2s3m0_sdi>;
    //rockchip,capture-only;
};

&i2c2 {
    clock-frequency = <100000>;
    status = "okay";
    pinctrl-0 = <&i2c2m1_xfer>;

    rk628_csi_v4l2: rk628_csi_v4l2@50 {
        reg = <0x50>;
        compatible = "rockchip,rk628-csi-v4l2";
        interrupt-parent = <&gpio4>;
        interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;

        pinctrl-names = "default";
        pinctrl-0 = <&hdmiin_gpios>;

        //enable-gpios = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
        reset-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>;
        //hdcp-enable = <1>;
    };
};

&rk628_csi_v4l2 {
    status = "okay";
    /*
    * If the hpd output level is inverted on the circuit,
    * the following configuration needs to be enabled.
    */
    /* hpd-output-inverted; */
    plugin-det-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>;
    power-gpios =  <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;

    rockchip,camera-module-index = <0>;
    rockchip,camera-module-facing = "back";
    rockchip,camera-module-name = "RK628-CSI";
    rockchip,camera-module-lens-name = "NC";

    port {
        hdmiin_out0: endpoint {
            remote-endpoint = <&mipi_in>;
            data-lanes = <1 2 3 4>;
        };
    };
};

&csi2_dphy_hw {
    status = "okay";
};

&csi2_dphy0 {
    status = "okay";
    ports {
        #address-cells = <1>;
        #size-cells = <0>;
        port@0 {
            reg = <0>;
            #address-cells = <1>;
            #size-cells = <0>;
            mipi_in: endpoint@0 {
                reg = <0>;
                remote-endpoint = <&hdmiin_out0>;
                data-lanes = <1 2 3 4>;
            };
        };
        port@1 {
            reg = <1>;
            #address-cells = <1>;
            #size-cells = <0>;
            csidphy0_out: endpoint@0 {
                reg = <0>;
                remote-endpoint = <&mipi_csi2_input>;
                data-lanes = <1 2 3 4>;
            };
        };
    };
};

&mipi_csi2 {
    status = "okay";
    ports {
        #address-cells = <1>;
        #size-cells = <0>;
        port@0 {
            reg = <0>;
            #address-cells = <1>;
            #size-cells = <0>;
            mipi_csi2_input: endpoint@1 {
                reg = <1>;
                remote-endpoint = <&csidphy0_out>;
                data-lanes = <1 2 3 4>;
            };
        };
        port@1 {
            reg = <1>;
            #address-cells = <1>;
            #size-cells = <0>;
            mipi_csi2_output: endpoint@0 {
                reg = <0>;
                remote-endpoint = <&cif_mipi_in>;
                data-lanes = <1 2 3 4>;
            };
        };
    };
};

&rkcif {
    status = "okay";
};

&rkcif_mipi_lvds {
    status = "okay";
    port {
        cif_mipi_in: endpoint {
            remote-endpoint = <&mipi_csi2_output>;
            data-lanes = <1 2 3 4>;
        };
    };
};

&rkcif_mmu {
    status = "okay";
};

&video_phy0 {
    status = "okay";
};

&video_phy1 {
    status = "disabled";
};

&pinctrl {
    hdmiin {
        hdmiin_gpios: hdmiin_gpios {
            rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>,
                            <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>,
                            <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
        };
    };
};