3519dv500接Lvds 只检测出了正常的宽，高检测不出来 问题

static combo_dev_attr_t g_lvds_4lane_thermo_640x512_12bit_dev2_attr = {
.devno = THERMO_LVDS_MIPI_DEV,
.input_mode = INPUT_MODE_LVDS,
.data_rate = MIPI_DATA_RATE_X1,
.img_rect = {0, 0, 1280, THERMO_LVDS_HEIGHT_512},
.lvds_attr = {
DATA_TYPE_RAW_16BIT,
OT_LVDS_WDR_MODE_NONE,
LVDS_SYNC_MODE_SOF,
{LVDS_VSYNC_NORMAL, 0, 0},
{LVDS_FID_NONE, 0},
LVDS_ENDIAN_BIG,
LVDS_ENDIAN_BIG,
{4, 5, 6, 7, -1, -1, -1, -1},
{
/ LVDS_SYNC_MODE_SOF slots: SOF, EOF, SOL, EOL. /
{{0xAB00, 0xB600, 0x8000, 0x9D00}},
{{0xAB00, 0xB600, 0x8000, 0x9D00}},
{{0xAB00, 0xB600, 0x8000, 0x9D00}},
{{0xAB00, 0xB600, 0x8000, 0x9D00}},
{{0xAB00, 0xB600, 0x8000, 0x9D00}},
{{0xAB00, 0xB600, 0x8000, 0x9D00}},
{{0xAB00, 0xB600, 0x8000, 0x9D00}},
{{0xAB00, 0xB600, 0x8000, 0x9D00}}

    }
}

};
/data # cat /proc/umap/mipi_rx

Module: [MIPI_RX], Build Time[Sep 26 2023, 21:36:38]

——-mipi lane divide mode——————————————————————————————————————————————-
mode lane divide
4 2+2+4

——-mipi dev attr——————————————————————————————————————————————————-
devno work_mode data_rate data_type wdr_mode img_x img_y img_w img_h
0 mipi X1 raw12 none 0 0 2688 1520
1 mipi X1 raw10 none 0 0 1280 1024
2 lvds X1 raw16 none 0 0 1280 512

——-mipi lane info——————————————————————————————————————————————————-
devno lane_id speed_mode
0 0, 2, -1, -1, -1, -1, -1, -1 LE1500Mbps
1 1, 3, -1, -1, -1, -1, -1, -1 LE1500Mbps
2 4, 5, 7, 6, -1, -1, -1, -1 LE1500Mbps

——-mipi clk info——————————————————————————————————————————————————-
devno enable
0 Y
1 Y
2 Y

———sns clk info——————————————————————————————————————————————————-
devno enable
0 Y

——-mipi phy data info———————————————————————————
phy_id lane_id phy_data mipi_data lvds_data freq
0 0, 1, 2, 3 0x00,0xfc,0x00,0x5e 0xc3,0x52,0x00,0x84 0x00,0xec,0x00,0x80 148MHZ
1 4, 5, 6, 7 0xba,0x08,0x02,0x02 0x00,0x00,0x00,0x00 0x80,0x80,0x80,0x80 n/a

——-mipi detect info——————————————————————————
devno vc width height
0 0 2688 1520
0 1 0 0
0 2 0 0
0 3 0 0
1 0 1280 1024
1 1 0 0
1 2 0 0
1 3 0 0

——-lvds detect info——————————————————————————
devno vc width height
2 0 1280 1
2 1 0 0
2 2 0 0
2 3 0 0

——-lvds lane detect info——————————————————————————
devno lane width height
2 4 320 1
2 5 320 1
2 7 320 1
2 6 320 1

——-phy cil err int info——————————————————————-
phy_id clk2_tmout clk_tmout lane0_tmout lane1_tmout lane2_tmout lane3_tmout clk2_esc clk_esc lane0_esc lane1_esc lane2_esc lane3_esc
0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0

——-mipi error int info1—————————————————————————————-
devno ecc2 vc0_crc vc1_crc vc2_crc vc3_crc vc0_ecc_correct vc1_ecc_correct vc2_ecc_correct vc3_ecc_correct
0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0

——-mipi error int info2—————————————————————————————-
devno vc0_frmnum vc1_frmnum vc2_frmnum vc3_frmnum vc0_frmmmatch vc1_frmmmatch vc2_frmmmatch vc3_frmmmatch
0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0

——-mipi error int info3—————————————————————————————-
devno data_fifo_rderr cmd_fifo_rderr vsync cmd_fifo_wrerr data_fifo_wrerr
0 0 0 -10 0 0
1 0 0 0 0 0

——-lvds error int info1—————————————————————————————-
devno vsync cmd_rderr cmd_wrerr pop_err stat_err
2 0 0 0 0 0

——-lvds error int info2—————————————————————————————-
devno link0_wrerr link1_wrerr link2_wrerr link0_rderr link1_rderr link2_rderr
2 0 0 0 0 0 0

——-lvds error int info3—————————————————————————————-
devno lane0_err lane1_err lane2_err lane3_err lane4_err lane5_err lane6_err lane7_err
2 0 0 0 0 0 0 0 0

——-align error int info———————————————————
devno fifo_fullerr lane0_err lane1_err lane2_err lane3_err lane4_err lane5_err lane6_err lane7_err
0 0 0 0 0 0 0 0 0 0
devno fifo_fullerr lane0_err lane1_err lane2_err lane3_err lane4_err lane5_err lane6_err lane7_err
1 1 0 1 0 0 0 0 0 0
devno fifo_fullerr lane0_err lane1_err lane2_err lane3_err lane4_err lane5_err lane6_err lane7_err
2 0 0 0 0 0 0 0 0 0

——-mipi dbg info——————————————————————————————————————————————————-
phyno skew_len0 skew_len1
0 0x00320000 0x00000000

这是我的lvds配置，跟Mip_rx打印，修改同步码顺序也不行，就能检测出正常的宽，有没有大佬提供一下思路，这是什么问题