VHDL代码VGA

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vga is
  port( clk,md:in std_logic;
       hs,vs,r,g,b:out std_logic);
end vga;
architecture behav of vga is
   signal hs1,vs1,fclk,cclk:std_logic;
   signal mmd:std_logic_vector(1 downto 0);
   signal fs:std_logic_vector (3 downto 0);
   signal cc:std_logic_vector (4 downto 0);
   signal ll:std_logic_vector (8 downto 0);
   signal grbx:std_logic_vector (3 downto 1);
   signal grby:std_logic_vector (3 downto 1);
   signal grbp:std_logic_vector (3 downto 1);
   signal grb2,grb3,grb1 :std_logic;
begin
   grb2<=(grbP(2)xor md ) and hs1 and vs1;
   grb3<=(grbp(3)xor md ) and hs1 and vs1;
   grb1<=(grbp(1) xor md) and hs1 and vs1;
   process(md)
   begin
      if  md'event and md='0' then
         if mmd="10"then mmd<="00";
           else mmd<=mmd+1;  end if;
       end if;
end process;
   process(mmd)
     begin
     if mmd="00"then grbp<=grbx;
     elsif mmd="01" then grbp<=grby;
     elsif mmd="10" then grbp<=grbx xor grby;
       else grbp<="000"; end if;
    end process;
process(clk)
   begin
      if clk'event and clk='1' then
         if cc=32 then  cc<="00000";
           else cc<=cc+1; end if;
      end if;
end process;
cclk<=cc(4);
process(cclk)
begin
    if cclk'event and cclk='0'  then
     if ll=490 then   ll<="000000000";
      else ll<=ll+1; end if;
    end if;
end process;
process(cc,ll)
begin
    if cc>23   then hs1<='0';
     else hs1<='1'; end if;
   if ll>479 then vs1<='0';
     else vs1<='1'; end if;
end process;

process(cc,ll)
begin
    if cc<3 then  grbx<="111";
    elsif cc<6 then grbx<="110";
    elsif cc<9 then grbx<="101";
    elsif cc<12 then grbx<="110";
    elsif cc<15  then grbx<="110";
    elsif cc<18 then grbx<="110";
    elsif cc<21 then grbx<="110";
    else grbx<="000"; end if;
     if ll<60 then grby<="111";
    elsif ll<120 then grby<="110";
    elsif ll<180 then grby<="101";
    elsif ll<240 then grby<="100";
    elsif ll<300 then grby<="011";
    elsif ll<360 then grby<="010";
    elsif ll<420 then grby<="001";
    else grby<="000"; end if;
end process;
hs<=hs1; vs<=vs1; r<=grb2;g<=grb3;b<=grb1;
end behav;