Hi3519dv500 4lane lvds接mipi_rx0上，phy_data显示有数据，但是lvds detect info一直为空，lvds lane detect info一直为1 0

4lane lvds的数据是fpga发送过来的4lane 16bit raw数据大端模式，lvds同步码为是海思默认的同步码

lvds combo_dev_attr_t设置如下

static combo_dev_attr_t g_lvds_8lane_attr = {
.devno = 0,
.input_mode = INPUT_MODE_LVDS,
.data_rate = MIPI_DATA_RATE_X1,
.img_rect = {0, 0, WIDTH_1280, HEIGHT_1024},
.lvds_attr = {
DATA_TYPE_RAW_16BIT,
OT_LVDS_WDR_MODE_NONE,
LVDS_SYNC_MODE_SAV,
{LVDS_VSYNC_NORMAL, 0, 0},
{LVDS_FID_NONE, TD_TRUE},
LVDS_ENDIAN_BIG,
LVDS_ENDIAN_BIG,
{0, 1, 2, 3, -1, -1, -1, -1},
{//同步码 需要和fpga对接
{
{0xab00,0xb600,0x8000,0x9d00},
{0xab00,0xb600,0x8000,0x9d00},
{0xab00,0xb600,0x8000,0x9d00},
{0xab00,0xb600,0x8000,0x9d00},
},
{
{0xab00,0xb600,0x8000,0x9d00},
{0xab00,0xb600,0x8000,0x9d00},
{0xab00,0xb600,0x8000,0x9d00},
{0xab00,0xb600,0x8000,0x9d00},
},
{
{0xab00,0xb600,0x8000,0x9d00},
{0xab00,0xb600,0x8000,0x9d00},
{0xab00,0xb600,0x8000,0x9d00},
{0xab00,0xb600,0x8000,0x9d00},
},
{
{0xab00,0xb600,0x8000,0x9d00},
{0xab00,0xb600,0x8000,0x9d00},
{0xab00,0xb600,0x8000,0x9d00},
{0xab00,0xb600,0x8000,0x9d00},
},
// {
// {0xab00,0xb600,0x8000,0x9d00},
// {0xab00,0xb600,0x8000,0x9d00},
// {0xab00,0xb600,0x8000,0x9d00},
// {0xab00,0xb600,0x8000,0x9d00},
// },
// {
// {0xab00,0xb600,0x8000,0x9d00},
// {0xab00,0xb600,0x8000,0x9d00},
// {0xab00,0xb600,0x8000,0x9d00},
// {0xab00,0xb600,0x8000,0x9d00},
// },
// {
// {0xab00,0xb600,0x8000,0x9d00},
// {0xab00,0xb600,0x8000,0x9d00},
// {0xab00,0xb600,0x8000,0x9d00},
// {0xab00,0xb600,0x8000,0x9d00},
// },
// {
// {0xab00,0xb600,0x8000,0x9d00},
// {0xab00,0xb600,0x8000,0x9d00},
// {0xab00,0xb600,0x8000,0x9d00},
// {0xab00,0xb600,0x8000,0x9d00},
// }
}
}
};

cat /proc/umap/mipi_rx 打印如下

Module: [MIPI_RX], Build Time[Jul 1 2025, 11:24:10]

——-mipi lane divide mode——————————————————————————————————————————————-
mode lane divide
1 4+4

——-mipi dev attr——————————————————————————————————————————————————-
devno work_mode data_rate data_type wdr_mode img_x img_y img_w img_h
0 lvds X1 raw16 none 0 0 1280 1024

——-mipi lane info——————————————————————————————————————————————————-
devno lane_id speed_mode
0 0, 1, 2, 3, -1, -1, -1, -1 LE1500Mbps

——-mipi clk info——————————————————————————————————————————————————-
devno enable
0 Y

———sns clk info——————————————————————————————————————————————————-
devno enable
0 Y

——-mipi phy data info———————————————————————————
phy_id lane_id phy_data mipi_data lvds_data freq
0 0, 1, 2, 3 0x07,0xe7,0x18,0x00 0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00 n/a
1 4, 5, 6, 7 0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00 n/a

——-lvds detect info——————————————————————————
devno vc width height
0 0 0 0
0 1 0 0
0 2 0 0
0 3 0 0

——-lvds lane detect info——————————————————————————
devno lane width height
0 0 1 0
0 1 1 0
0 2 1 0
0 3 1 0

——-phy cil err int info——————————————————————-
phy_id clk2_tmout clk_tmout lane0_tmout lane1_tmout lane2_tmout lane3_tmout clk2_esc clk_esc lane0_esc lane1_esc lane2_esc lane3_esc
0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0

——-lvds error int info1—————————————————————————————-
devno vsync cmd_rderr cmd_wrerr pop_err stat_err
0 0 0 0 0 0

——-lvds error int info2—————————————————————————————-
devno link0_wrerr link1_wrerr link2_wrerr link0_rderr link1_rderr link2_rderr
0 0 0 0 0 0 0

——-lvds error int info3—————————————————————————————-
devno lane0_err lane1_err lane2_err lane3_err lane4_err lane5_err lane6_err lane7_err
0 0 0 0 0 0 0 0 0

——-align error int info———————————————————
devno fifo_fullerr lane0_err lane1_err lane2_err lane3_err lane4_err lane5_err lane6_err lane7_err
0 0 0 0 0 0 0 0 0 0

——-mipi dbg info——————————————————————————————————————————————————-
phyno skew_len0 skew_len1